Google's Frozen v2 AI Chip: Everything You Need to Know (2026 Guide)

I've spent the better part of this year watching five companies — Google, Amazon, Microsoft, Meta, and OpenAI — quietly build the same conclusion into silicon: renting someone else's chips to run your AI models is no longer a viable long-term strategy. Frozen v2 is Google's latest and strangest entry into that race, and it's the one most likely to be misunderstood, because the headline number (a reported 6–10x efficiency gain) is the least interesting thing about it. The interesting thing is what Google is willing to give up to get there, and why it's giving that up right now, in the middle of what's arguably the roughest stretch Google's AI division has had since Gemini launched. This is the cornerstone guide. Everything below is built from confirmed reporting, Google's own public statements, and verifiable industry context — not speculation dressed up as insight. Where something is uncertain, I'll tell you it's uncertain. Where it connects to a bigger story, I'll show you the connection. Bookmark this one; the supporting pieces on TPU economics, the custom-silicon race, and what this means for Gemini's roadmap will all link back here. Quick Facts Metric Detail Chip codename Frozen v2 Developer Google (Alphabet) First reported by The Information, July 20, 2026 Confirmed by Google No — neither confirmed nor denied Claimed efficiency gain 6–10x more tokens per unit of power vs. current TPUs Design scope Built specifically for Gemini's architecture, not general-purpose Reported deployment target As early as 2028 Relationship to TPUs Complementary, reportedly a smaller-scale trial run, not a replacement Market reaction Alphabet (GOOGL) shares rose roughly 3% on the report Reported trade-off Tied to Gemini's current architecture; less flexible than general-purpose chips What Is Frozen v2? Frozen v2 is the internal codename for a server chip Alphabet is reportedly developing to make its Gemini AI models run substantially more efficiently. The report originated with The Information, a subscription tech-industry publication known for sourcing directly from inside major tech companies, and was picked up and confirmed independently by outlets including Bloomberg, TechCrunch, and CNBC over the following day. None of them have published a leaked spec sheet, a die shot, or a manufacturing partner — which tells you this is still an early-stage project being talked about internally, not a chip that's sampling in a lab with a launch date on a roadmap slide. When TechCrunch asked Google directly about the project, the company's response was carefully non-committal: its teams are "constantly researching and experimenting with new innovations to deliver maximum performance and efficiency," and "not every project moves into production." That's a company confirming that something like this is plausible without confirming that this specific thing is real — standard practice for unannounced hardware, and worth remembering every time you see the 6–10x figure repeated as fact rather than as a reported claim. Here's the mechanism, as described in the reporting: Frozen v2 would permanently embed parts of Gemini's model architecture directly into the chip's silicon, rather than running Gemini as software on a flexible, general-purpose processor. That's a fundamentally different design philosophy from anything Google has shipped publicly before, including its own TPUs — and it's worth slowing down to understand exactly what that means, because "hardwiring a model into a chip" sounds like marketing language until you unpack it. The Direct Answer Google is reportedly building a chip called Frozen v2 that embeds parts of Gemini's architecture directly into silicon, aiming for 6–10x better power efficiency than its current TPUs. It's unconfirmed by Google, reportedly two years or more from deployment, and designed to complement — not replace — Google's existing TPU lineup. The bigger story isn't the chip itself; it's why Google needed this news to land the week of its earnings report. How a Chip Can Have a Model "Built Into" It To understand why this is unusual, it helps to know the three broad categories AI hardware falls into today. General-purpose processors — CPUs, and to a lesser extent GPUs — are built to do almost anything. They execute instructions one step at a time (or in parallel batches, for GPUs), interpreting whatever software you throw at them. This flexibility is expensive: every operation requires the chip to figure out what to do, fetch the relevant data, and move it around before doing the actual math. For AI workloads, that overhead adds up fast. Domain-specific chips — this is where TPUs, Trainium, Maia, and MTIA all live. These are Application-Specific Integrated Circuits (ASICs) built around the mathematical operations that dominate neural networks — matrix multiplication, in particular. They're not flexible enough to run a spreadsheet or a web browser, but they're built to run any neural network efficiently, whethe